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| Name: cpuid | Distribution: SUSE Linux Enterprise 15 |
| Version: 20221201 | Vendor: SUSE LLC <https://www.suse.com/> |
| Release: 150300.3.4.1 | Build date: Tue Mar 7 09:35:37 2023 |
| Group: System/Management | Build host: sheep66 |
| Size: 556855 | Source RPM: cpuid-20221201-150300.3.4.1.src.rpm |
| Packager: https://www.suse.com/ | |
| Url: http://etallen.com/cpuid.html | |
| Summary: x86 CPU identification tool | |
cpuid executes the CPUID instruction on x86-family CPUs and decodes the results into English descriptions. It knows about Intel, AMD, and Cyrix CPUs, and is fairly complete.
GPL-2.0-or-later
* Mon Dec 05 2022 valentin.lefebvre@suse.com
- Update to release 20221201
* Clarified synth decoding for Intel Xeon D-1700.
* Added uarch & synth decoding for AMD 4800S Desktop Kit, based on
instlatx64 sample.
* Added uarch decoding for AMD Genoa A1, based on instlatx64 sample
* Added uarch decoding for (0,6),(12,15) Emerald Rapids, from LX*.
* Added synth & uarch decoding for (10,15),(10,1) Bergamo.
* Added 0x8000000a/edx bits: ROGPT, VNMI, IBS virtualization.
* Added 0x8000001b/eax bit: IBS L3 miss filtering support.
* Added 0x8000001f/eax bits: RMPQUERY instruction support,
VMPL supervisor shadow stack support, VMGEXIT parameter support,
virtual TOM MSR support, IBS virtual support for SEV-ES guests,
SMT protection support, SVSM communication page MSR support,
VIRT_RMPUPDATE & VIRT_PSMASH MSR support.
* Added 0x80000020/0/ecx bit: L3 range reservation support.
* Added 0x80000021/eax bits: automatic IBRS,
CPUID disable for non-privileged.
* Added 0x80000022/eax bit: AMD LBR & PMC freezing.
* Added 0x80000022/ebx field: number of LBR stack entries.
* Added 0x80000023 leaf: Multi-Key Encrypted Memory Capabilities.
* Added 0x80000026 leaf: AMD Extended CPU Topology.
* cpuid.c: use lseek64 and cpuset_setaffinity, Added 0x80000022/eax
AMD LBR V2 flag, from LX*.
* Thu Oct 13 2022 valentin.lefebvre@suse.com
- Update to release 20221003
* Added synth decoding for AMD Ryzen (Phoenix E0, Storm Peak A1)
* Added synth & uarch synth decoding for
* (0,6),(11,5) Intel Meteor Lake
* (0,6),(11,6) Intel Grand Ridge (Crestmont)
* (0,6),(11,14) Intel Granite Rapids
* Renamed 7/0/eax enh hardware feedback to just "Thread
Director".
* Added 7/1/eax instructions.
* Added 0x12/0/eax SGX ENCLU EDECCSA flag.
* Added 0x23 Architecture Performance Monitoring Extended leaf
decoding.
* Corrected AVX512IFMA description: integer FMA, not just FMA.
- Release 20220927
* Added synth decoding for (10,15),(6,1) Raphael
* Fixed title for AMD 0x8000001a leaf: Performance Optimization
identifiers.
* Sat Aug 13 2022 jengelh@inai.de
- Update to release 20220812
* Corrected (synth) decoding for (0,6),(8,6) Intel Snow
Ridge/Parker Ridge.
* Added 8000000a/edx X2AVIC flag
* Generalized (0,6),(8,14),9,YP stepping case to include
Pentium 4425Y, from instlatx64 sample.
* Added support for hypervisor+3/ecx (Microsoft) flags.
* Thu Feb 24 2022 andreas.stieger@gmx.de
- update to 20220224:
* Support for AMD Rembrandt E1
* Add hypervisor+4/eax (Xen) expanded destination id bit
* Correction for Alder Lake, Rocket Lake decoding
* Multiple detection and decodings updated
* Mon Nov 15 2021 andreas.stieger@gmx.de
- update to 20211114:
* Many updated and added identified CPU models and variants
* Updated hypervisor support
* Thu Oct 08 2020 josef.moellers@suse.com
- Update to 20201006:
Added "Sapphire Rapids", "Golden Cove", "Rocket Lake", "Cato",
14nm "Zen", "Tiger Lake-U B0", "Elkhart Lake B0", "Alder Lake",
"Comet Lake", "Picasso A1", "Renoir A1", "Zhaoxin KaiXian KX-6000",
as well as some additional decoding of supported features.
[cpuid-20201006.src.tar.gz, jsc#sle-13189]
* Tue Apr 28 2020 andreas.stieger@gmx.de
- update to 20200427:
* Add synth decoding for AMD Steppe Eagle/Crowned Eagle
(Puma 2014 G-Series), based on instlatx64 sample
* Add 7/0/edx SERIALIZE & TSXLDTRK bit descriptions
* Add 0xf/1/eax Counter width & overflow flag
* Add 0x10/3/ecx per-thread MBA controls flag
* Add 0x8000001f fields
* Add AMD 24594 & 40332 docs
* Correct field lengths in 14/0 and 14/1 subleafs so that
columns line up
* Add CC150 (Coffee Lake R0) synth decoding, based on
instlatx64 example
* Add Jasper Lake A0 stepping (from Coreboot*)
* Update 1/ebx "cpu count" to modern terminology: "maximum
addressible IDs for CPUs in pkg" to avoid user confusion
* Update 4/eax CPU & core count terminology in the same way
* Fri Mar 06 2020 jengelh@inai.de
- Update to release 20200211
* Zhaoxin decoding
* Name enhancements for models from AMD, VIA, Intel, NSC
* Added SEV cpuid bit.
* Fri Jan 17 2020 josef.moellers@suse.com
- Upgrade to release 20200116
many changes in Changelog: many new flags added.
Also added support for Cyrix MediaGX, Matisse B0 stepping,
Hygon CPUs.
[cpuid-20200116.src.tar.gz]
* Sat May 19 2018 jengelh@inai.de
- Update to new upstream release 20180519
* Added 7/ecx bit 7: CET_SS and 7/edx bit 20: CET_IBT fields.
* Added 7/ecx bit 16: 5-level paging.
* Improved 14/0/ecx descriptions.
* Added hypervisor leaf descriptions from Microsoft's
Hypervisor Top Level Functional Specification (Released
Version 5.0b).
* Added CPUID features documented in PPR for AMD Family 17h
Model 01h B1 (54945 Rev 1.14):
* Added PCOMMIT to 7/ebx: PCOMMIT instruction (a deprecated
instruction).
* Added bits to 80000001/ecx (amd).
* Added bits to 80000007/edx, 8000000a/edx, 8000001a/eax,
8000001b/eax.
* Added 80000007/ebx, 80000007/ecx, 80000008/ebx.
* Added tentative 8000001f descriptions.
* Fri Apr 20 2018 josef.moellers@suse.com
- Update to new upstream release 20180419
* Added synth decoding for AMD Zen, Pentium Silver (Gemini
Lake), Xeon Scalable (Bronze, Silver, Gold, Platinium)
(Skylake), Core X-Series (Skylake-X), Bay Trail D0, Bay Trail
A0, Xeon E7-4800/8800 (Broadwell-EX B0), Xeon D-1500N
(Broadwell-DE A1), Bay Trail-I (E3800), Avoton C0 stepping.
* Corrected synth decoding for Bay Trail-M C0 steppings.
* Added new Intel 1b leaf from Intel Architecture.
* Added various bit fields.
* Mon Jan 23 2017 jengelh@inai.de
- Update to new upstream release 20170122
* Added synth decoding for Intel Knights Landing B0.
* Added new synth decodings for Intel Kaby Lake.
* Fixed synth decodings for AMD Steamroller and Jaguar.
* Added synth decodings for AMD Puma and Excavator.
* For (6,15),(0,2) Piledriver processors, detect FX series and
report it as Vishera instead of Abu Dhabi/Seoul/Delhi.
* Added general microarchitecure names for AMD (e.g.
Piledriver) in addition to specific core names (e.g. Trinity)
for later generation processors. If I have trouble
remembering these, it seems likely other people do too.
* Added synth decoding for Quark X1000.
* Added Intel Atom Z2760 (Clover Trail).
* Added extra synth decodings for some Ivy Bridge and Sandy
Bridge processors.
* Fri Dec 02 2016 jengelh@inai.de
- Update to new upstream release 20161201
* Fixed bugs in the subleaf walks for 0x8000001d (AMD cache
information) and 0x40000003 (Xen hypervisor information) because
the code for them was under wholly the wrong loops.
* Tue Nov 15 2016 jengelh@inai.de
- Update to new upstream release 20161114
* cpuid.c: Added -l/--leaf and -s/--subleaf options to cause
cpuid to dump just the specified leaf and subleaf. If
- s/--subleaf is not specified, it is assumed to be 0. The
intended purpose for this is to display raw dumps of
not-yet-supported leaves.
* cpuid.c: Added AVX512DQ, AVX512IFMA, AVX512BW, AVX512VL, and
CLWB decoding to 7/ebx.
* cpuid.c: Added AVX512VBMI to 7/ecx.
* cpuid.c: Added print_f_0_edx to show L3 cache QoS monitoring
support.
* cpuid.c: Added total & local bandwidth monitoring to 0xf/1/edx.
* cpuid.c: Added 0x15/ecx nominal core crystal clock decoding.
* cpuid.c: In print_17_0_ebx, corrected reversed scheme
encodings.
* cpuid.c: Added synth decoding for Xeon D-1500 (Broadwell-DE) Y0
stepping.
* cpuid.c: Added synth decoding comment about Braswell D1
stepping, but its stepping number is not documented.
* cpuid.c: Added synth decoding for (0,6),(8,14) Kaby Lake
processors.
* cpuid.c: Added synth decoding for Apollo Lake processors.
* cpuid.c: Added vague synth decoding for (0,6),(9,14) Kaby Lake
processors.
* cpuid.c: Add AVX512_4VNNIW & AVX512_4FMAPS flags.
* cpuid.c: Add Knights Mill (KNM) CPUID.
* Tue Aug 30 2016 jengelh@inai.de
- Update to new upstream release 20160814
* cpuinfo2cpuid: Added a script that takes input from a
/proc/cpuinfo file and converts it into suitable input to
cpuid. The information that cpuid is capable of producing based
on this very limited input information is slight, but
apparently there is interest in getting the synthesized (synth)
leaf from this.
* Support SGX, MPX, BNDLDX/BNDSTX, RDPID, and IA32_XSS PT state.
* Add information for Skylake, Broadwell, Broadwell-E and -EX
processors, Atom C2000 (Avoton) with A0/A1 steppings, Atom
Z3n00 (Bay Trail) stepping 1, Xeon D-1500 (Broadwell-DE) V2
stepping, corrected Atom Z8000 (Cherry Trail), added Atom S1200
(Centerton) and VIA Eden.
* Sat Nov 07 2015 jengelh@inai.de
- Update to new upstream release 20151017
* Updated synth decoding for Broadwell processors.
* Added 0xd leaf field.
* Updated and expanded 0x14 leaf fields.
* Added synth decoding for Intel Xeon E7 v2 (Ivy Bridge-EX).
* Added synth decoding for Intel Core i5/i7 (Skylake).
* Decode new leaf 2 cache descriptors: 6a, 6b, 6c, 6d.
* added synth decoding for Knights Landing.
* Added new & missing decodings for: 4/ecx, 6/eax, 7/ebx, 7/ecx.
* Renamed 0xf leaves to include "Monitoring".
* Added 0x10 leaves for QoS Enforcement.
* Added new leaf 2 cache meanings: 0x1d, 0x24, 0xa0, 0xc3.
* Added missing i7 synth decoding for (0,6),(3,14).
* Corrected Atom Z3000 model & stepping which were bafflingly
wrong: (0,6)(3,5),1 -> (0,6)(3,7),8.
* Corrected other Bay Trail stepping names for Celeron/Pentium
N and J series.
* Added synth decoding for Intel Xeon Phi (Knights Corner).
* Added synth decoding for Intel Atom C2000 (Avoton).
* Added synth decoding for Intel Xeon E5-x600 (Haswell-EP).
* Added synth decoding for Intel Xeon E5-[48]800 (Haswell-EP).
* Added synth decoding for Intel Core M (Broadwell-Y).
* Added synth decoding for Intel Xeon D-1500 (Broadwell-DE).
* Added synth decoding for Intel i7-5000 Extreme (Haswell R2).
* Added synth decoding for Intel Atom Z8000 (Cherry Trail).
* Added synth decoding for Intel Pentium/Celeron N3000
* Tue Jun 09 2015 jengelh@inai.de
- Update to new upstream release 20150606
* Support for several leaf updates, including information on
XSAVEC, XGETBV, and XSAVES/XRSTORS instructions. Decoding for
more Haswell processors, Broadwell, Cherry Trail, and Avoton.
- %doc is already implicit for manpages
/usr/bin/cpuid /usr/bin/cpuinfo2cpuid /usr/share/doc/packages/cpuid /usr/share/doc/packages/cpuid/ChangeLog /usr/share/licenses/cpuid /usr/share/licenses/cpuid/LICENSE /usr/share/man/man1/cpuid.1.gz
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